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/*	 * turn off dog, see C18P3	 */	ldr	r0, =pWTCON	mov	r1, #0x0	str	r1, [r0]	/*	 * C14	 * mask all IRQs by setting all bits in the INTMR - default	 */	mov	r1, #0xffffffff	ldr	r0, =INTMSK	str	r1, [r0]	ldr	r1, =0x7fff	ldr	r0, =INTSUBMSK	str	r1, [r0]	/*	 * FCLK:HCLK:PCLK = 1:4:8	 * because we will set fclk, hclk, pclk, at different speed,	 * the CLKDIVEN should be changed, and the C15 should be set	 * please see Chapter 7 Page 9	 */	ldr	r0, =CLKDIVN	mov	r1, #5	str	r1, [r0]	/*	 * orr	r0, r0, #R1_nF:OR:R1_iA	 * This strange thing comes from the C15 co-processor	 */	mrc	p15, 0, r0, c1, c0, 0	orr	r0, r0, #0xc0000000	mcr	p15, 0, r0, c1, c0, 0	/*	 * set mpll to 405Mhz, see C7P21	 */	ldr	r0, =MPLLCON	mov	r1, #0x21	and	r1, r1, #MPLL405	str	r1, [r0]

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